Active matrix emissive micro led display

ABSTRACT

A display panel and a method of forming a display panel are described. The display panel may include a thin film transistor substrate including a pixel area and a non-pixel area. The pixel area includes an array of bank openings and an array of bottom electrodes within the array of bank openings. An array of micro LED devices are bonded to the corresponding array of bottom electrodes within the array of bank openings. An array of top electrode layers are formed electrically connecting the array of micro LED devices to a ground line in the non-pixel area.

RELATED APPLICATIONS

This application is a continuation application of co-pending U.S. patentapplication Ser. No. 13/842,721, filed Mar. 15, 2013, which is acontinuation-in-part of co-pending U.S. patent application Ser. No.13/710,443 filed on Dec. 10, 2012, both of which are incorporated hereinby reference.

BACKGROUND

1. Field

Embodiments of the present invention relate to display systems. Moreparticularly embodiments of the present invention relate to a groundingstructure for an active matrix display panel.

2. Background Information

Flat panel displays are gaining popularity in a wide range of electronicdevices. Common types of flat panel displays include active matrixdisplays and passive matrix displays. Each pixel in an active matrixdisplay panel is driven by active driving circuitry, while each pixel ina passive matrix display panel does not use such driving circuitry.High-resolution color display panels, such as modern computer displays,smart phones and televisions typically use an active matrix displaypanel structure for better image quality.

One kind of display panel that is finding commercial application is anactive matrix organic light emitting diode (AMOLED) display panel. FIG.1 is a top view illustration of a top emission AMOLED display panel.FIG. 2 is a cross-sectional side view illustration of FIG. 1 taken alongline X-X in the pixel area 104 and line Y-Y crossing the ground ring 116in the non-pixel area. The AMOLED display panel 100 illustrated in FIGS.1-2 generally includes a thin film transistor (TFT) substrate 102supporting a pixel area 104 and non-pixel area outside of the pixel area102. A TFT substrate 102 is also referred to as a backplane. A TFTsubstrate which has been further processed to additionally include thepixel area and non-pixel area is also often referred to as a backplane.Two primary TFT substrate technologies used in AMOLEDs includepolycrystalline silicon (poly-Si) and amorphous silicon (a-Si). Thesetechnologies offer the potential for fabricating the active matrixbackplanes at low temperatures (below 200° C.) directly onto flexibleplastic substrates for producing flexible AMOLED displays. The pixelarea 104 generally includes pixels 106 and subpixels 108 arranged in amatrix, and a set of TFTs and capacitors connected to each subpixel fordriving and switching the subpixels. The non-pixel area generallyincludes a data driver circuit 110 connected to a data line of eachsubpixel to enable data signals (Vdata) to be transmitted to thesubpixels, a scan driver circuit 112 connected to scan lines of thesubpixels to enable scan signals (Vscan) to be transmitted to thesubpixels, a power supply line 114 to transmit a power signal (Vdd) tothe TFTs, and a ground ring 116 to transmit a ground signal (Vss) to thearray of subpixels. As shown, the data driver circuit, scan drivercircuit, power supply line, and ground ring are all connected to aflexible circuit board (FCB) 113 which includes a power source forsupplying power to the power supply line 114 and a power source groundline electrically connected to the ground ring 116.

In the exemplary AMOLED backplane configuration an organic thin film 120and top electrode 118 are deposited over every subpixel 108 in the pixelarea 104. The organic thin film 120 may include multiple layers such asa hole injection layer, hole transport layer, light emitting layer,electron transport layer, and electron injection layer. The multiplelayers of the organic thin film 120 are typically formed over the entirepixel area 104, however, the light emitting layer is often depositedwith aid of a shadow mask only within the subpixel openings 127 and onthe bottom electrode layer 124 corresponding to the emission area forthe array of subpixels 108. A top electrode layer 118 is then depositedover the organic thin film within both the pixel area 104 and alsowithin the non-pixel area so that the top electrode 118 layer overlapsthe ground ring 116 in the in order to transfer the ground signal to thearray of subpixels. In this manner, each of the subpixels 108 can beindividually addressed with the corresponding underlying TFT circuitrywhile a uniform ground signal is supplied to the top of the pixel area104.

In the particular implementation illustrated, the TFT substrate 102includes a switching transistor T1 connected to a data line 111 from thedata driver circuit 110 and a driving transistor T2 connected to a powerline 115 connected to the power supply line 114. The gate of theswitching transistor T1 may also be connected to a scan line (notillustrated) from the scan driver circuit 112. A planarization layer 122is formed over the TFT substrate, and openings are formed to expose theTFT working circuitry. As illustrated, a bottom electrode layer 124 isformed on the planarization layer in electrical connection with the TFTcircuitry. Following the formation of the electrode layer a pixeldefining layer 125 is formed including an array of subpixel openings 127corresponding to the emission area for the array of subpixels 108,followed by deposition of the organic layer 120 and top electrode layer118 over the patterned pixel defining layer, and within subpixelopenings 127 of the patterned pixel defining layer 125. The topelectrode layer 118 additionally is formed in the non-pixel area and inelectrical connection with the ground ring 116.

The planarization layer 122 may function to prevent (or protect) theorganic layer 120 and the bottom electrode layer 124 from shorting dueto a step difference. Exemplary planarization layer 122 materialsinclude benzocyclobutene (BCB) and acrylic. The pixel defining layer 125can be formed of a material such as polyimide. The bottom electrode 124is commonly formed on indium tin oxide (ITO), ITO/Ag, ITO/Ag/ITO,ITO/Ag/indium zinc oxide (IZO), or ITO/Ag alloy/ITO. The top electrodelayer 118 is formed of a transparent material such as ITO for topemission.

While AMOLED display panels generally consume less power than liquidcrystal display (LCD) panels, an AMOLED display panel can still be thedominant power consumer in battery-operated devices. To extend batterylife, it is necessary to reduce the power consumption of the displaypanel.

SUMMARY OF THE INVENTION

A display panel and a method of forming a display panel are described.In an embodiment a display panel includes a TFT substrate including apixel area and a non-pixel area. For example, the non-pixel area maysurround the pixel area. The pixel area includes an array of bankopenings and an array of bottom electrodes within the array of bankopenings. The array of bottom electrodes may be formed on sidewalls ofthe corresponding array of bank openings, and may be reflective to thevisible wavelength. In an embodiment a post of solder material is formedon the bottom electrode within each bank opening in order to aid thebonding of a micro LED device to the bottom electrode. A ground line isformed in the non-pixel area. In an embodiment, the ground line is aground ring. In an embodiment a patterned insulator layer covers thearray of bottom electrodes, and an array of openings is formed in thepatterned insulator exposing the array of bottom electrodes. In thismanner, the patterned insulator layer may cover the edges of the arrayof bottom electrodes.

In an embodiment, an array of micro LED devices are on the array ofbottom electrodes within the corresponding array of bank openings. Forexample, the micro LED devices may be vertical micro LED devices, andmay have a maximum width of 1 μm-100 μm. A transparent passivation layercan be formed spanning sidewalls of the array of micro LED deviceswithout completely covering a top conductive contact of each micro LEDdevice. In an embodiment, an array of top electrode layers are formedover the array of micro LED devices electrically connecting the array ofmicro LED devices to the ground line. For example, each top electrodelayer may span over a single row of micro LED devices. Each topelectrode may span over a plurality of rows of micro LED devices. In anembodiment, the each top electrode layer is electrically connected tothe ground ring on opposite sides of the pixel area. The top electrodelayers may also be formed of a transparent or semi-transparent materialsuch as PEDOT or ITO.

In an embodiment, a method of forming a display panel includestransferring an array of micro LED devices from a carrier substrate to abackplane that comprises a TFT substrate including a pixel area and anon-pixel area, where the pixel area includes an array of bank openingsand an array of bottom electrodes within the array of bank openings. TheTFT substrate also includes a ground line in the non-pixel area. In anembodiment, an array of separate top electrode layers are formed overthe array micro LED devices electrically connecting the array of microLED devices to the ground line. In an embodiment, top electrode layersare formed by ink jet printing or screen printing. In an embodiment, theground line is a ground ring and the array of separate top electrodelayers span between opposite sides of the ground ring. In accordancewith embodiments of the invention, each top electrode layer may spanover one or more rows of micro LED devices. For example, each topelectrode layer may span over a single row of micro LED device, or mayspan over a plurality of rows of micro LED devices. It is not requiredfor the top electrode layers to completely cover the pixel area of theTFT substrate.

In an embodiment, transfer of the array of micro LED device is performedwith electrostatic principles using an array of electrostatic transferheads. Furthermore, bonding of the array of micro LED devices mayinclude the formation of an inter-metallic compound, and may includeliquefying an array of bonding layers formed on the array of bottomelectrodes. Bonding and liquefying may be accomplished in part by thetransfer of thermal energy from the array of electrostatic transferheads to the array of bonding layers formed on the array of bottomelectrodes.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top view illustration of a top emission AMOLED displaypanel.

FIG. 2 is a side-view illustration of the top emission AMOLED displaypanel of FIG. 1 taken along lines X-X and Y-Y.

FIG. 3A is a top view illustration of an active matrix display panel inaccordance with an embodiment of the invention.

FIG. 3B is a side-view illustration of the active matrix display panelof FIG. 3A taken along lines X-X and Y-Y in accordance with anembodiment of the invention.

FIG. 3C is a side-view illustration of the active matrix display panelof FIG. 3A taken along lines X-X and Y-Y in accordance with anembodiment of the invention in which a ground ring is formed within apatterned bank layer.

FIG. 3D is a side-view illustration of the active matrix display panelof FIG. 3A taken along lines X-X and Y-Y in accordance with anembodiment of the invention in which a ground ring is formed below apatterned bank layer.

FIGS. 4A-4H are cross-sectional side view illustrations for a method oftransferring an array of micro LED devices to a TFT substrate inaccordance with an embodiment of the invention.

FIGS. 5A-5C are top view illustrations for a sequence of transferring anarray of micro LED devices with different color emissions in accordancewith an embodiment of the invention.

FIG. 6A is a top view illustration of an active matrix display panelafter the formation of a top electrode layer in accordance with anembodiment.

FIG. 6B is a top view illustration of an active matrix display panelafter the formation of separate top electrode layers in accordance withan embodiment.

FIG. 6C is a side-view illustration of the active matrix display panelof either FIG. 6A or FIG. 6B taken along lines X-X and Y-Y in accordancewith an embodiment of the invention.

FIG. 6D is a side-view illustration of the active matrix display panelof either FIG. 6A or FIG. 6B taken along lines X-X and Y-Y in accordancewith an embodiment of the invention.

FIG. 7 is a schematic illustration of a display system in accordancewith an embodiment of the invention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiments of the present invention relate to display systems. Moreparticularly embodiments of the present invention relate to an activematrix display panel including emissive micro LEDs.

In one aspect, embodiments of the invention describe an active matrixdisplay panel including wafer-based emissive micro LED devices. A microLED device combines the performance, efficiency, and reliability ofwafer-based LED devices with the high yield, low cost, mixed materialsof thin film electronics used to form AMOLED backplanes. The terms“micro” device or “micro” LED structure as used herein may refer to thedescriptive size of certain devices or structures in accordance withembodiments of the invention. As used herein, the terms “micro” devicesor structures are meant to refer to the scale of 1 to 100 μm. However,it is to be appreciated that embodiments of the present invention arenot necessarily so limited, and that certain aspects of the embodimentsmay be applicable to larger, and possibly smaller size scales. In anembodiment, a display panel is similar to a typical OLED display panel,with a micro LED device having replaced the organic layer of the OLEDdisplay panel in each subpixel. Exemplary micro LED devices which may beutilized with some embodiments of the invention are described in U.S.patent application Ser. No. 13/372,222, U.S. patent application Ser. No.13/436,260, U.S. patent application Ser. No. 13/458,932, U.S. patentapplication Ser. No. 13/711,554, and U.S. patent application Ser. No.13/749,647 all of which are incorporated herein by reference. The microLED devices are highly efficient at light emission and consume verylittle power (e.g., 250 mW for a 10 inch diagonal display) compared to5-10 watts for a 10 inch diagonal LCD or OLED display, enablingreduction of power consumption of the display panel.

In various embodiments, description is made with reference to figures.However, certain embodiments may be practiced without one or more ofthese specific details, or in combination with other known methods andconfigurations. In the following description, numerous specific detailsare set forth, such as specific configurations, dimensions andprocesses, etc., in order to provide a thorough understanding of thepresent invention. In other instances, well-known semiconductorprocesses and manufacturing techniques have not been described inparticular detail in order to not unnecessarily obscure the presentinvention. Reference throughout this specification to “one embodiment”means that a particular feature, structure, configuration, orcharacteristic described in connection with the embodiment is includedin at least one embodiment of the invention. Thus, the appearances ofthe phrase “in one embodiment” in various places throughout thisspecification are not necessarily referring to the same embodiment ofthe invention. Furthermore, the particular features, structures,configurations, or characteristics may be combined in any suitablemanner in one or more embodiments.

The terms “spanning”, “over”, “to”, “between” and “on” as used hereinmay refer to a relative position of one layer with respect to otherlayers. One layer “spanning”, “over” or “on” another layer or bonded“to” or in “contact” with another layer may be directly in contact withthe other layer or may have one or more intervening layers. One layer“between” layers may be directly in contact with the layers or may haveone or more intervening layers.

Referring now to FIGS. 3A-3B an embodiment is illustrated in which abackplane similar to an AMOLED backplane is modified to receive emissivemicro LED devices rather than an organic emission layer. FIG. 3A is atop view illustration of an active matrix display panel in accordancewith an embodiment, and FIG. 3B is a side-view illustration of theactive matrix display panel of FIG. 3A taken along lines X-X and Y-Y inaccordance with an embodiment of the invention. In such an embodiment,the underlying TFT substrate 102 can be similar to those in a typicalAMOLED backplane described with regard to FIGS. 1-2 including workingcircuitry (e.g. T1, T2) and planarization layer 122. Openings 131 may beformed in the planarization layer 122 to contact the working circuitry.The working circuitry can include traditional 2T1C (two transistors, onecapacitor) circuits including a switching transistor, a drivingtransistor, and a storage capacitor. It is to be appreciated that the2T1C circuitry is meant to be exemplary, and that other types ofcircuitry or modifications of the traditional 2T1C circuitry arecontemplated in accordance with embodiments of the invention. Forexample, more complicated circuits can be used to compensate for processvariations of the driver transistor and the light emitting device, orfor their instabilities. Furthermore, while embodiments of the inventionare described and illustrated with regard to top gate transistorstructures in the TFT substrate 102, embodiments of the invention alsocontemplate the use of bottom gate transistor structures Likewise, whileembodiments of the invention are described and illustrated with regardto a top emission structure, embodiments of the invention alsocontemplate the use of bottom, or both top and bottom emissionstructures. In addition, embodiments of the invention are described andillustrated below specifically with regard to a high side driveconfiguration including a ground ring. In a high side driveconfiguration a LED may be on the drain side of a PMOS driver transistoror a source side of an NMOS driver transistor so that the circuit ispushing current through the p-terminal of the LED. Embodiments of theinvention are not so limited may also be practiced with a low side driveconfiguration in which case the ground ring become the power line in thepanel and current is pulled through the n-terminal of the LED.

A patterned bank layer 126 including bank openings 148 is then formedover the planarization layer 122. Bank layer 126 may be formed by avariety of techniques such as ink jet printing, screen printing,lamination, spin coating, CVD, and PVD. Bank layer 126 may be may beopaque, transparent, or semi-transparent to the visible wavelength. Banklayer 126 may be formed of a variety of insulating materials such as,but not limited to, photodefinable acrylic, photoresist, silicon oxide(SiO₂), silicon nitride (SiN_(x)), poly(methyl methacrylate) (PMMA),benzocyclobutene (BCB), polyimide, acrylate, epoxy, and polyester. In anembodiment, bank player is formed of an opaque material such as a blackmatrix material. Exemplary insulating black matrix materials includeorganic resins, glass pastes, and resins or pastes including a blackpigment, metallic particles such as nickel, aluminum, molybdenum, andalloys thereof, metal oxide particles (e.g. chromium oxide), or metalnitride particles (e.g. chromium nitride).

In accordance with embodiments of the invention, the thickness of thebank layer 126 and width of the bank openings 128 described with regardto the following figures may depend upon the height of the micro LEDdevice to be mounted within the opening, height of the transfer headstransferring the micro LED devices, and resolution. In an embodiment,the resolution, pixel density, and subpixel density of the display panelmay account for the width of the bank openings 128. For an exemplary 55inch television with a 40 PPI (pixels per inch) and 211 μm subpixelpitch, the bank opening 128 width may be anywhere from a few microns to206 μm to account for an exemplary 5 μm wide surrounding bank structure.For an exemplary display panel with 440 PPI and a 19 μm subpixel pitch,the bank opening 128 width may be anywhere from a few microns to 15 μmto account for an exemplary 5 μm wide surrounding bank structure. Widthof the bank structure (i.e. between bank openings 128) may be anysuitable size, so long as the structure supports the required processesand is scalable to the required PPI.

In accordance with embodiments of the invention, the thickness of thebank layer 126 is not too thick in order for the bank structure tofunction. Thickness may be determined by the micro LED device height anda predetermined viewing angle. For example, where sidewalls of the bankopenings 128 make an angle with the planarization layer 122, shallowerangles may correlate to a wider viewing angle of the system. In anembodiment, exemplary thicknesses of the bank layer 126 may be between 1μm-50 μm.

A patterned conductive layer is then formed over the patterned banklayer 126. Referring to FIG. 3B, in one embodiment the patternedconductive layer includes bottom electrodes 142 formed within the bankopenings 148 and in electrical contact with the working circuitry. Thepatterned conductive layer may also optionally include the ground ring116. As used herein the term ground “ring” does not require a circularpattern, or a pattern that completely surrounds an object. Rather, theterm ground “ring” means a pattern that at least partially surrounds thepixel area on three sides. In addition, while the following embodimentsare described and illustrated with regard to a ground ring 116, it is tobe appreciated that embodiments of the invention can also be practicedwith a ground line running along one side (e.g. left, right, bottom,top), or two sides (a combination of two of the left, right, bottom,top) of the pixel area. Accordingly, it is to be appreciated that in thefollowing description the reference to and illustration of a ground ringcould potentially be replaced with a ground line where systemrequirements permit.

The patterned conductive layer may be formed of a number of conductiveand reflective materials, and may include more than one layer. In anembodiment, a patterned conductive layer comprises a metallic film suchas aluminum, molybdenum, titanium, titanium-tungsten, silver, or gold,or alloys thereof. The patterned conductive layer may include aconductive material such as amorphous silicon, transparent conductiveoxides (TCO) such as indium-tin-oxide (ITO) and indium-zinc-oxide (IZO),carbon nanotube film, or a transparent conducting polymer such aspoly(3,4-ethylenedioxythiophene) (PEDOT), polyaniline, polyacetylene,polypyrrole, and polythiophene. In an embodiment, the patternedconductive layer includes a stack of a conductive material and areflective conductive material. In an embodiment, the patternedconductive layer includes a 3-layer stack including top and bottomlayers and a reflective middle layer wherein one or both of the top andbottom layers are transparent. In an embodiment, the patternedconductive layer includes a conductive oxide-reflective metal-conductiveoxide 3-layer stack. The conductive oxide layers may be transparent. Forexample, the patterned conductive layer may include an ITO-silver-ITOlayer stack. In such a configuration, the top and bottom ITO layers mayprevent diffusion and/or oxidation of the reflective metal (silver)layer. In an embodiment, the patterned conductive layer includes aTi—Al—Ti stack, or a Mo—Al—Mo—ITO stack. In an embodiment, the patternedconductive layer includes a ITO—Ti—Al—Ti—ITO stack. In an embodiment,the patterned conductive layer is 1 μm or less in thickness. Thepatterned conductive layer may be deposited using a suitable techniquesuch as, but not limited to, PVD.

Following the formation of bottom electrodes 142 and ground ring 116, aninsulator layer 146 may then optionally be formed over the TFT substrate102 covering the sidewalls of the pattered conductive layer. Theinsulator layer 146 may at least partially cover the bank layer 126 andthe reflective layer forming the bottom electrodes 142, and optionallythe ground ring 116.

In an embodiment, the insulator layer 146 is formed by blanketdeposition using a suitable technique such as lamination, spin coating,CVD, and PVD, and then patterned using a suitable technique such aslithography to form openings exposing the bottom electrodes 142, andoptionally openings 130 exposing the ground ring 116. In an embodiment,ink jet printing or screen printing may be used to form the insulatorlayer 146 and optionally openings 130 without requiring lithography.Insulator layer 146 may be formed of a variety of materials such as, butnot limited to, SiO₂, SiN_(x), PMMA, BCB, polyimide, acrylate, epoxy,and polyester. For example, the insulator layer 146 may be 0.5 μm thick.The insulator layer 146 may be transparent or semi-transparent whereformed over the reflective layer on sidewalls of bottom electrode 142within the bank openings 128 as to not significantly degrade lightemission extraction of the completed system. Thickness of the insulatorlayer 146 may also be controlled to increase light extractionefficiency, and also to not interfere with the array of transfer headsduring transfer of the array of light emitting devices to the reflectivebank structure. As will become more apparent in the followingdescription, the patterned insulator layer 146 is optional, andrepresents one manner for electrically separating, or passivating thesidewalls of conductive layers.

In the embodiment illustrated in FIG. 3B, the bottom electrodes 142 andground ring 116 can be formed of the same conductive layer. In anotherembodiment, the ground ring 116 can be formed of a conductive materialdifferent from the bottom electrodes 142. For example, ground ring 116may be formed with a material having a higher conductivity than thebottom electrodes 142. In another embodiment, ground ring 116 can alsobe formed within different layers from the bottom electrodes. FIGS.3C-3D illustrate embodiments where the ground ring 116 can be formedwithin or below the patterned bank layer 126. For example, in theembodiment illustrated in FIG. 3C, openings 130 may be formed throughthe patterned bank layer 126 when forming the ground ring 116. In theembodiment illustrated in FIG. 3D, openings 130 may be formed throughthe patterned bank layer 126 and planarization layer 122 to contact theground ring 116 which may have been formed during formation of theworking circuitry of the TFT substrate 102. In such an embodiment theconductive layer used to form the bottom electrode 142 may alsooptionally also be formed within the opening 130 to further enableelectrical contact of the top electrode layer yet to be formed with theground ring 116 through openings 130. Accordingly, it is to beappreciated that the embodiments illustrated in FIGS. 3A-3D are notlimiting and that a number of possibilities exist for forming the groundring 116, as well as openings 130 to expose the ground ring 116.

Still referring to embodiments illustrated in FIG. 3B-3D, a bondinglayer 140 may be formed on the bottom electrode layer 142 to facilitatebonding of a micro LED device. In an embodiment, the bonding layer 140is selected for its ability to be inter-diffused with a bonding layer onthe micro LED device (yet to be placed) through bonding mechanisms suchas eutectic alloy bonding, transient liquid phase bonding, or solidstate diffusion bonding as described in U.S. patent application Ser. No.13/749,647. In an embodiment, the bonding layer 140 has a meltingtemperature of 250° C. or lower. For example, the bonding layer 140 mayinclude a solder material such as tin (232° C.) or indium (156.7° C.),or alloys thereof. Bonding layer 140 may also be in the shape of a post,having a height greater than width. In accordance with some embodimentsof the invention, taller bonding layers 140 may provide an additionaldegree of freedom for system component leveling, such as planarity ofthe array of micro LED devices with the TFT substrate during the microLED device transfer operation and for variations in height of the microLED devices, due to the change in height of the liquefied bonding layersas they spread out over the surface during bonding, such as duringeutectic alloy bonding and transient liquid phase bonding. The width ofthe bonding layers 140 may be less than a width of a bottom surface ofthe micro LEDs to prevent wicking of the bonding layers 140 around thesidewalls of the micro LEDs and shorting the quantum well structures.

FIGS. 4A-4H are cross-sectional side view illustrations for a method oftransferring an array of micro LED devices to the TFT substrate 102 inaccordance with an embodiment of the invention. Referring to FIG. 4A, anarray of transfer heads 302 supported by a transfer head substrate 300are positioned over an array of micro LED devices 400 supported on acarrier substrate 200. A heater 306 and heat distribution plate 304 mayoptionally be attached to the transfer head substrate 300. A heater 204and heat distribution plate 202 may optionally be attached to thecarrier substrate 200. The array of micro LED devices 400 are contactedwith the array of transfer heads 302, as illustrated in FIG. 4B, andpicked up from the carrier substrate 200 as illustrated in FIG. 4C. Inan embodiment, the array of micro LED devices 400 are picked up with anarray of transfer heads 302 operating in accordance with electrostaticprinciples, that is, they are electrostatic transfer heads.

FIG. 4D is a cross-sectional side view illustration of a transfer head302 holding a micro LED device 400 over a TFT substrate 102 inaccordance with an embodiment of the invention. In the embodimentillustrated, the transfer head 302 is supported by a transfer headsubstrate 300. As described above, a heater 306 and heat distributionplate 304 may optionally be attached to the transfer head substrate toapply heat to the transfer head 302. A heater 152 and heat distributionplate 150 may also, or alternatively, optionally be used to transferheat to the bonding layer 140 on the TFT substrate 102 and/or optionalbonding layer 410 on a micro LED device 400 described below.

Still referring to FIG. 4D, a close-up view of an exemplary micro LEDdevice 400 is illustrated in accordance with an embodiment. It is to beappreciated, that the specific micro LED device 400 illustrated isexemplary and that embodiments of the invention are not limited. In theparticular embodiment illustrated, the micro LED device 400 includes amicro p-n diode 450 and a bottom conductive contact 420. A bonding layer410 may optionally be formed below the bottom conductive contact 420,with the bottom conductive contact 420 between the micro p-n diode 450and the bonding layer 410. In an embodiment, the micro LED device 400further includes a top conductive contact 452. In an embodiment, themicro p-n diode 450 includes a top n-doped layer 414, one or morequantum well layers 416, and a lower p-doped layer 418. In otherembodiments, the arrangement of n-doped and p-doped layers can bereversed. The micro p-n diodes can be fabricated with straight sidewallsor tapered sidewalls. In certain embodiments, the micro p-n diodes 450possess outwardly tapered sidewalls 453 (from top to bottom). In certainembodiments, the micro p-n diodes 450 possess inwardly tapered sidewall(from top to bottom). The top and bottom conductive contacts 420, 452.For example, the bottom conductive contact 420 may include an electrodelayer and a barrier layer between the electrode layer and the optionalbonding layer 410. The top and bottom conductive contacts 420, 452 maybe transparent to the visible wavelength range (e.g. 380 nm-750 nm) oropaque. The top and bottom conductive contacts 420, 452 may optionallyinclude a reflective layer, such as a silver layer. The micro p-n diodeand conductive contacts may each have a top surface, a bottom surfaceand sidewalls. In an embodiment, the bottom surface 451 of the micro p-ndiode 450 is wider than the top surface of the micro p-n diode, and thesidewalls 453 are tapered outwardly from top to bottom. The top surfaceof the micro p-n diode 450 may be wider than the bottom surface of thep-n diode, or approximately the same width. In an embodiment, the bottomsurface 451 of the micro p-n diode 450 is wider than the top surface ofthe bottom conductive contact 420. The bottom surface of the micro p-ndiode may also be approximately the same width as the top surface of thebottom conductive contact 420. In an embodiment, the micro p-n diode 450is several microns thick, such as 3 μm or 5 μm, the conductive contacts420, 452 are 0.1 μm-2 μm thick, and the optional bonding layer 410 is0.1 μm-1 μm thick. In an embodiment, a maximum width of each micro LEDdevice 400 is 1-100 μm, for example, 30 μm, 10 μm, or 5 μm. In anembodiment, the maximum width of each micro LED device 400 must complywith the available space in the bank opening 128 for a particularresolution and PPI of the display panel.

FIG. 4E is a cross-sectional side view illustration of an array oftransfer heads holding an array micro LED devices 400 over a TFTsubstrate 102 accordance with an embodiment of the invention. FIG. 4E issubstantially similar to the structure illustrated in FIG. 4D with theprimary difference being the illustration of the transfer of an array ofmicro LED devices as opposed to a single micro LED device within thearray of micro LED devices.

Referring now to FIG. 4F the TFT substrate 102 is contacted with thearray of micro LED devices 400. In the embodiment illustrated,contacting the TFT substrate 102 with the array of micro LED devices 400includes contacting bonding layer 140 with a micro LED device bondinglayer 410 for each respective micro LED device. In an embodiment, eachmicro LED device bonding layer 410 is wider than a corresponding bondinglayer 140. In an embodiment energy is transferred from the electrostatictransfer head assembly and through the array of micro LED devices 400 tobond the array of micro LED devices 400 to the TFT substrate 102. Forexample, thermal energy may be transferred to facilitate several typesof bonding mechanisms such as eutectic alloy bonding, transient liquidphase bonding, and solid state diffusion bonding. The transfer ofthermal energy may also be accompanied by the application of pressurefrom the electrostatic transfer head assembly.

Referring to FIG. 4G, in an embodiment, the transfer of energy liquefiesbonding layer 140. The liquefied bonding layer 140 may act as a cushionand partially compensate for system uneven leveling (e.g. nonplanarsurfaces) between the array of micro devices 400 and the TFT substrateduring bonding, and for variations in height of the micro LED devices.In the particular implementation of transient liquid phase bonding theliquefied bonding layer 140 inter-diffuses with the micro LED devicebonding layer 410 to form an inter-metallic compound layer with anambient melting temperature higher than the ambient melting temperatureof the bonding layer 140. Accordingly, transient liquid phase bondingmay be accomplished at or above the lowest liquidus temperature of thebonding layers. In some embodiments of the invention, the micro LEDdevice bonding layer 410 is formed of a material having a meltingtemperature above 250° C. such as bismuth (271.4° C.), or a meltingtemperature above 350° C. such as gold (1064° C.), copper (1084° C.),silver (962° C.), aluminum (660° C.), zinc (419.5° C.), or nickel (1453°C.), and the TFT substrate bonding layer 140 has a melting temperaturebelow 250° C. such as tin (232° C.) or indium (156.7° C.).

In this manner, the substrate 150 supporting the TFT substrate 102 canbe heated to a temperature below the melting temperature of the bondinglayer 140, and the substrate 304 supporting the array of transfer headsis heated to a temperature below the melting temperature of bondinglayer 410, but above the melting temperature of bonding layer 140. Insuch an embodiment, the transfer of heat from the electrostatic transferhead assembly through the array of micro LED devices 400 is sufficientto form the transient liquid state of bonding layer 140 with subsequentisothermal solidification as an inter-metallic compound. While in theliquid phase, the lower melting temperature material both spreads outover the surface and diffused into a solid solution of the highermelting temperature material or dissolves the higher melting temperaturematerial and solidifies as an inter-metallic compound. In a specificembodiment, the substrate 304 supporting the array of transfer heads isheld at 180° C., bonding layer 410 is formed of gold, and bonding layer140 is formed of indium.

Following the transfer of energy to bond the array of micro LED devices400 to the TFT substrate, the array of micro LED devices 400 arereleased onto the receiving substrate and the array of electrostatictransfer heads are moved away as illustrated in FIG. 4H. Releasing thearray of micro LED devices 400 may be accomplished with a variety ofmethods including turning off the electrostatic voltage sources,lowering the voltage across the electrostatic transfer head electrodes,changing a waveform of an AC voltage, and grounding the voltage sources.

Referring now to FIGS. 5A-5C, a sequence of transferring an array ofmicro LED devices 400 with different color emissions is illustrated inaccordance with an embodiment of the invention. In the particularconfiguration illustrated in FIG. 5A, a first transfer procedure hasbeen completed for transferring an array of red-emitting micro LEDdevices 400R from a first carrier substrate to the TFT substrate 102.For example, where the micro LED devices 400R are designed to emit a redlight (e.g.620-750 nm wavelength) the micro p-n diode 450 may include amaterial such as aluminum gallium arsenide (AlGaAs), gallium arsenidephosphide (GaAsP), aluminum gallium indium phosphide (AlGaInP), andgallium phosphide (GaP). Referring to FIG. 5B, a second transferprocedure has been completed for transferring an array of green-emittingmicro LED devices 400G from a second carrier substrate to the TFTsubstrate 102. For example, where the micro LED devices 400G aredesigned to emit a green light (e.g.495-570 nm wavelength) the micro p-ndiode 450 may include a material such as indium gallium nitride (InGaN),gallium nitride (GaN), gallium phosphide (GaP), aluminum gallium indiumphosphide (AlGaInP), and aluminum gallium phosphide (AlGaP). Referringto FIG. 5C, a third transfer procedure has been completed fortransferring an array of blue-emitting micro LED devices 400B from athird carrier substrate to the TFT substrate 102. For example, where themicro LED devices 400B are designed to emit a blue light (e.g.450-495 nmwavelength) the micro p-n diode 450 may include a material such asgallium nitride (GaN), indium gallium nitride (InGaN), and zinc selenide(ZnSe).

In accordance with embodiments of the invention, the transfer heads areseparated by a pitch (x, y, and/or diagonal) that matches a pitch of thebank openings on the backplane corresponding to the pixel or subpixelarray. Table 1 provides a list of exemplary implementations inaccordance with embodiments of the invention for various red-green-blue(RGB) displays with 1920×1080 p and 2560×1600 resolutions. It is to beappreciated that embodiments of the invention are not limited to RGBcolor schemes or the 1920×1080 p or 2560×1600 resolutions, and that thespecific resolution and RGB color scheme is for illustrational purposesonly.

TABLE 1 Pixel Sub-Pixel Pixels Display Pitch pitch per inch Possibletransfer head Substrate (x, y) (x, y) (PPI) array pitch 55″  (634 μm,(211 μm, 40 X: Multiples or fractions 1920 × 1080 634 μm) 634 μm) of 211μm Y: Multiples or fractions of 634 μm 10″  (85 μm, (28 μm, 299 X:Multiples or fractions 2560 × 1600 85 μm) 85 μm) of 28 μm Y: Multiplesor fractions of 85 μm 4″ (78 μm, (26 μm, 326 X: Multiples or fractions 640 × 1136 78 μm) 78 μm) of 26 μm Y: Multiples or fractions of 78 μm 5″(58 μm, (19 μm, 440 X: Multiples or fractions 1920 × 1080 58 μm) 58 μm)of 19 μm Y: Multiples or fractions of 58 μm

In the above exemplary embodiments, the 40 PPI pixel density maycorrespond to a 55 inch 1920×1080 p resolution television, and the 326and 440 PPI pixel density may correspond to a handheld device withRETINA (RTM) display. In accordance with embodiments of the invention,thousands, millions, or even hundreds of millions of transfer heads canbe included in a micro pick up array of a mass transfer tool dependingupon the size of the micro pick up array. In accordance with embodimentsof the invention, a 1 cm×1.12 cm array of transfer heads can include 837transfer heads with a 211 μm, 634 μm pitch, and 102,000 transfer headswith a 19 μm, 58 μm pitch.

The number of micro LED devices picked up with the array of transferheads may or may not match the pitch of transfer heads. For example, anarray of transfer heads separated by a pitch of 19 μm picks up an arrayof micro LED devices with a pitch of 19 μm. In another example, an arrayof transfer heads separated by a pitch of 19 μm picks up an array ofmicro LED devices with a pitch of approximately 6.33 μm. In this mannerthe transfer heads pick up every third micro LED device for transfer tothe backplane. In accordance with some embodiments, the top surface ofthe array of light emitting micro devices is higher than the top surfaceof the insulator layer 146 so as to prevent the transfer heads frombeing damaged by or damaging the insulator layer (or any interveninglayer) on the backplane during placement of the micro LED devices withinbank openings.

FIG. 6A is a top view illustration of an active matrix display panel inaccordance with an embodiment after the formation of a top electrodelayer. FIG. 6B is a top view illustration of an active matrix displaypanel in accordance with an embodiment after the formation of separatetop electrode layers. FIGS. 6C-6D are side-view illustrations of theactive matrix display panel of either FIG. 6A or FIG. 6B taken alonglines X-X and Y-Y in accordance with embodiments of the invention. Inaccordance with the embodiments illustrated in FIGS. 6A-6B, one or moretop electrode layers 118 are formed over the pixel area 104 includingthe array of micro LED devices 400 as well as in the non-pixel area andoverlapping the ground ring 116.

Referring now to FIGS. 6C-6D, prior to forming the one or more topelectrode layers 118 the micro LED devices 400 are passivated within thebank openings 128 in order to prevent electrical shorting between thetop and bottom electrode layers 118, 142, or shorting at the one or morequantum wells 416. As illustrated, after the transfer of the array microLED devices 400, a passivation layer 148 may be formed around thesidewalls of the micro LED devices 400 within the array of bank openings128. In an embodiment, where the micro LED devices 400 are vertical LEDdevices, the passivation layer 148 covers and spans the quantum wellstructure 416. The passivation layer 148 may also cover any portions ofthe bottom electrode layer 142 not already covered by the optionalinsulator layer 146 in order to prevent possible shorting. Accordingly,the passivation layer 148 may be used to passivate the quantum wellstructure 416, as well as the bottom electrode layer. In accordance withembodiments of the invention, the passivation layer 148 is not formed onthe top surface of the micro LED devices 400, such as top conductivecontact 452. In one embodiment, a plasma etching process, e.g. O₂ or CF₄plasma etch, can be used after forming the passivation layer 148 to etchback the passivation layer 148, ensuring the top surface of the microLED devices 400, such as top conductive contacts 452, are exposed toenable the top conductive electrode 118 layers 118 to make electricalcontact with the micro LED devices 400.

In accordance with embodiments of the invention, the passivation layer148 may be transparent or semi-transparent to the visible wavelength soas to not significantly degrade light extraction efficiency of thecompleted system. Passivation layer may be formed of a variety ofmaterials such as, but not limited to epoxy, acrylic (polyacrylate) suchas poly(methyl methacrylate) (PMMA), benzocyclobutene (BCB), polyimide,and polyester. In an embodiment, passivation layer 148 is formed by inkjet printing or screen printing around the micro LED devices 400.

In the particular embodiment illustrated in FIG. 6C, the passivationlayer 148 is only formed within the bank openings 128. However, this isnot required, and the passivation layer 148 may be formed on top of thebank structure layer 126. Furthermore, the formation of insulator layer146 is not required, and passivation layer 148 can also be used toelectrically insulate the conductive layers. As shown in the embodimentillustrated in FIG. 6D, the passivation layer 148 may also be used topassivate sidewalls of the conductive layer forming the bottom electrode142. In an embodiment, passivation layer 148 may optionally be used topassivate ground ring 116. In accordance with some embodiments, theformation of openings 130 can be formed during the process of ink jetprinting or screen printing the passivation layer 148 over the groundring 116. In this manner, a separate patterning operation may not berequired to form the openings 130.

In accordance with some embodiments of the invention a canal 151, orwell structure, can be formed within the bank layer 126 as illustratedin FIG. 6D in order to capture or prevent the passivation layer 148 fromspreading excessively and overflowing over the ground tie lines 149,particularly when the passivation layer 148 is formed using a solventsystem such as with ink jet printing or screen printing. Accordingly, insome embodiments, a canal 151 is formed within the bank layer 126between the bank opening 128 and an adjacent ground tie line 144.

Still referring to FIGS. 6C-6D, after formation of passivation layer 148one or more top conductive electrode layers 118 are formed over eachmicro LED device 400 and in electrical contact with the top contactlayer 452, if present. Depending upon the particular application in thefollowing description, top electrode layers 118 may be opaque,reflective, transparent, or semi-transparent to the visible wavelength.For example, in top emission systems the top electrode layer 118 may betransparent, and for bottom emission systems the top electrode layer maybe reflective. Exemplary transparent conductive materials includeamorphous silicon, transparent conductive oxides (TCO) such asindium-tin-oxide (ITO) and indium-zinc-oxide (IZO), carbon nanotubefilm, or a transparent conductive polymer such aspoly(3,4-ethylenedioxythiophene) (PEDOT), polyaniline, polyacetylene,polypyrrole, and polythiophene. In an embodiment, the top electrodelayer 118 includes nanoparticles such as silver, gold, aluminum,molybdenum, titanium, tungsten, ITO, and IZO. In a particularembodiment, the top electrode layer 118 is formed by ink jet printing orscreen printing ITO or a transparent conductive polymer such as PEDOT.Other methods of formation may include chemical vapor deposition (CVD),physical vapor deposition (PVD), spin coating. The top electrode layer118 may also be reflective to the visible wavelength. In an embodiment,a top conductive electrode layer 118 comprises a reflective metallicfilm such as aluminum, molybdenum, titanium, titanium-tungsten, silver,or gold, or alloys thereof, for example for use in a bottom emissionsystem.

Referring back to FIG. 6A again, in the particular embodimentillustrated a top electrode layer 118 is formed over the pixel area 104including the array of micro LED devices 400 as well as in the non-pixelarea and overlapping the ground ring 116. The top electrode layer 118may also be formed within the openings 130, if present, and over theground ring 116.

FIG. 6B illustrates an alternative embodiment in which separate topelectrode layers 118 are formed connecting one or more rows of micro LEDdevices 400 with the ground ring. In the particular embodimentillustrated, the top electrode layers 118 provide the electrical pathfrom a micro LED device 400 to the ground ring. It is not required forthe top electrode layers 118 to cover the entire pixel area 104, or theentire bank opening 128. In the particular embodiment illustrated, eachtop electrode layer 118 is connected to opposite sides of the groundring 116 and runs horizontally across the TFT substrate connecting asingle row of micro LEDs 400. However, this particular configuration isexemplary and a number of different arrangements are possible. Forexample, a single top electrode layer 118 may run over, and electricallyconnect an n-number of rows of micro LEDs to the ground ring. In anotherembodiment, the top electrode layers 118 are only connected to one sideof the ground ring 116, or ground line. As illustrated in FIGS. 6A-6B,ink jet line width for the top electrode layers 118 can vary dependingupon application. For example, the line width may approach that of thepixel area 104. Alternatively, the line width may be minimal. Forexample, line widths as low as approximately 15 μm may be accomplishedwith commercially available ink jet printers. Accordingly, the linewidth of the top electrode layers 118 may be more or less than themaximum width of the micro LED devices.

In one aspect, the particular embodiment illustrated in FIG. 6B may beparticularly suitable for localized formation of the top electrodelayers 118 with ink jet printing or screen printing. Conventional AMOLEDbackplane processing sequences such as those used for the fabrication ofthe display panels in FIGS. 1-2 typically blanket deposit the topelectrode layer in deposition a chamber, followed by singulation of theindividual backplanes from a larger substrate. In accordance with someembodiments, the display panel\backplane 100 is singulated from a largersubstrate prior to transferring the array of micro LED devices 400. Inan embodiment, ink jet printing or screen printing provides a practicalapproach for patterning the individual top electrode layers 118 withoutrequiring a separate mask layer for each separate display panelbackplane 100.

While not illustrated separately it is to be appreciated that theembodiments illustrated in FIGS. 6A-6D are combinable with thealternative opening configurations included in FIGS. 3C-3D.

FIG. 7 illustrates a display system 700 in accordance with anembodiment. The display system houses a processor 710, data receiver720, a display panel 100, such as any of the display panels describedabove. The data receiver 720 may be configured to receive datawirelessly or wired. Wireless may be implemented in any of a number ofwireless standards or protocols including, but not limited to, Wi-Fi(IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long termevolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA,TDMA, DECT, Bluetooth, derivatives thereof, as well as any otherwireless protocols that are designated as 3G, 4G, 5G, and beyond.

Depending on its applications, the display system 700 may include othercomponents. These other components include, but are not limited to,memory, a touch-screen controller, and a battery. In variousimplementations, the display system 700 may be a television, tablet,phone, laptop, computer monitor, kiosk, digital camera, handheld gameconsole, media display, ebook display, or large area signage display.

In utilizing the various aspects of this invention, it would becomeapparent to one skilled in the art that combinations or variations ofthe above embodiments are possible for integrating micro LED devicesinto an active matrix display panel. While the above embodiments havebeen described with regard to a top emission structure, embodiments ofthe invention are also applicable to bottom emission structures. Forexample, rather than locating the bank openings 128 or subpixel openings127 above the TFT circuitry, the openings could be located adjacent theTFT circuitry on lower layers in the TFT substrate 102. Similarly, whiletop gate transistor structures have been described, embodiments of theinvention may also be practiced with bottom gate transistor structures.Furthermore, while embodiments of the invention have been described andillustrated with regard to a high side drive configuration, embodimentsmay also be practiced with a low side drive configuration in which theground ring described above becomes the power line in the panel.Although the present invention has been described in language specificto structural features and/or methodological acts, it is to beunderstood that the invention defined in the appended claims is notnecessarily limited to the specific features or acts described. Thespecific features and acts disclosed are instead to be understood asparticularly graceful implementations of the claimed invention usefulfor illustrating the present invention.

What is claimed is:
 1. A display panel comprising: a lower conductivelayer including a ground line; a planarization layer over the lowermetal layer; an opening in the planarization layer; a patterned topconductive layer over the planarization layer, wherein the patterned topconductive layer includes: an array of bottom electrodes; and a groundcontact within the opening in the planarization layer and in electricalcontact with the ground line; a corresponding plurality of lightemitting diodes (LEDs) bonded to the plurality of bottom electrodes; andone or more top electrode layers on and in electrical contact with theplurality of LEDs and the ground contact.
 2. The display panel of claim1, wherein each LED comprises an inorganic semiconductor-based p-ndiode.
 3. The display panel of claim 2, wherein each LED is a verticalLED with a maximum width of 1 μm-100 μm.
 4. The display panel of claim3, wherein each bottom electrode is independently addressable.
 5. Thedisplay panel of claim 4, wherein each LED device has a maximum width of1 μm-20 μm.
 6. The display panel of claim 3, wherein the one or more topelectrode layers includes a single top electrode layer on and inelectrical contact with the plurality of LEDs and the ground contact. 7.The display panel of claim 3, wherein the one or more top electrodelayers includes a plurality of top electrode layers.
 8. The displaypanel of claim 7, wherein each top electrode layer spans over aplurality of rows of LEDs.
 9. The display panel of claim 7, wherein eachtop electrode layer spans over a single row of LEDs.
 10. The displaypanel of claim 3, further comprising a patterned bank layer including anarray of bank openings over the planarization layer, wherein each LED iswithin a corresponding bank opening.
 11. The display panel of claim 10,further comprising a passivation layer spanning sidewalls of the arrayof LEDs within the array of bank openings, wherein the passivation layerdoes not completely cover a top conductive contact of each LED.
 12. Thedisplay panel of claim 11, wherein the one or more top electrode layersspans across the passivation layer.
 13. The display panel of calm 11,wherein the passivation layer is transparent to the visible wavelengthspectrum.
 14. The display panel of claim 11, wherein the patterned banklayer is opaque.
 15. The display panel of claim 11, wherein thepassivation layer spans a quantum well structure for each LED.
 16. Thedisplay panel of claim 11, wherein the opening is formed in thepatterned bank layer and the planarization layer, and the ground contactis within the opening in both the patterned bank layer and theplanarization layer, and is in electrical contact with the ground line.17. The display panel of claim 3, wherein each LED is bonded to acorresponding bottom electrode with an In—Au compound.
 18. The displaypanel of claim 3, wherein the one or more top electrode layers comprisesa transparent conductive oxide.
 19. The display panel of claim 18,wherein the transparent conductive oxide is indium-tin oxide.
 20. Thedisplay panel of claim 3, wherein the one or more top electrode layerscomprises a transparent conductive polymer.